Data (information) stored in integrated circuit-type memory devices is susceptible to corruption, due, in part, to the bombardment of the devices by alpha particles. To provide a means for error detection and correction, often times, redundant data is stored. Rather than storing an exact copy of the data, commonly, "check bits" generated in accordance with the data encoding scheme known as "Hamming code" are stored. From a "word" of data, each of the check bits is generated by "EXORing" (gating together in exclusive OR gates) selected bits from the data word. When a data word is retrieved from the memory devices, the corresponding check bits are also retrieved. From the retrieved data word and the corresponding retrieved check bits, in accordance with the Hamming code scheme, "syndromes" are generated, by EXORing selected bits of the retrieved data word with the corresponding bits of the retrieved check bits. The syndromes are used for detecting and correcting error(s) in the retrieved data word.
Typical of prior art-type error detection and correction devices are devices of the type which are designated IDT 49C460 by Integrated Device Technology, Inc. (and AM 29C660 by Advanced Micro Devices, Inc.) and which are described in the corresponding data sheets and on pages 8-235 to 8-255 of the data book by Integrated Device Technology, Inc. entitled "High Performance CMOS 1988 Data Book." The above-mentioned (49C460) devices are intended for use with data words which are 32 binary bits in length. In addition, the above-mentioned devices have provisions for "word expansion" (means by which one device may be configured, with a similar device, in cascade, for use with data words which are 64 binary bits in length). (A 64-bit, prior-art-type, error detection and correction system is illustrated in FIG. 1 of the drawing generally designated by the number 100.) When so expanded, one of two similar devices is configured as a "lower 32-bit" device (represented in the figure by a block 110) and the other one of the two devices is configured as an "upper 32-bit" device (represented in the figure by a block 112). The lower 32-bit device (110) is configured, with a set of 32 data inputs/outputs of the device connected, each to a corresponding line of a lower 32-bit data bus 120; with a set of eight, device check-bit inputs connected, each to a corresponding line of an eight-line syndrome/check-bit bus 122; and with a set of eight, device syndrome/check-bit outputs connected, each to a corresponding line of an eight-line inter-device bus 124. The upper 32-bit device (112) is configured with tile set of 32 data device inputs/outputs connected, each to a corresponding line of an upper 32-bit data bus 130; with the set of eight, device check-bit inputs connected, each to a corresponding line of the eight lines of the inter-device bus (124); and with the set of eight, device syndrome/check bit outputs connected, each to a corresponding line of the eight lines of the syndrome/check bit bus 122.
When a (64-bit) word of data is being stored in memory, signals representing the lower 32-bits of the data word are developed on the lower 32-bit data bus (120) and signals representing the upper 32-bits of the data word are developed on the upper 32-bit data bus (130). Responsive to the signals representing the lower 32-bits of the data word (developed on lower 32-bit data bus 120) the lower 32-bit device (110) generates partial check bits and develops on the inter-device bus (124) signals representing the generation partial check bits. Responsive to the signals representing the upper 32-bits of the data word (developed on upper 32-bit data bus 130) and to the signals representing the generation partial check bits (generated by lower 32-bit device 110 on inter-device bus 124) the upper 32-bit device 1112) generates final check bits and develops on the syndrome/check bit bus (122) signals representing the final check bits. The final check bits (represented by the signals generated by upper 32-bit device 112 on syndrome/check bit bus 122) are stored with the (64-bits of the) data word in memory.
When a (64-bit) word of data is being retrieved from memory, signals representing the lower 32-bits of the retrieved data word are developed on the lower 32-bit data bus (120); signals representing the upper 32-bits of the retrieved data word are developed on the upper 32-bit data bus (130); and signals representing the corresponding, retrieved, check bits are developed on the syndrome/check bit bus (122). Responsive to certain control signals, the lower 32-bit device (110) is operative to latch the state of the signals representing the lower 32-bits of the retrieved data word (developed on lower 32-bit data bus 120) and to latch the state of the signals representing the retrieved check bits (developed on syndrome/check bit bus 122). In addition, responsive to the state of the latched, lower 32-bits of the retrieved data word the lower 32-bit device (110) generates (new) correction partial check bits. Further, responsive to the (new) correction partial check bits and to the state of the latched, retrieved, check bits, the lower 32-bit device (110) is operative to generate correction partial syndrome bits and to develop, on the inter-device bus (124), signals representing the correction partial syndrome bits. Responsive to the control signals, the upper 32-bit device (112) is operative to latch the state of the signals representing the upper 32-bits of the retrieved data word (developed on upper 32-bit data bus 130). In addition, responsive to the state of the latched, upper 32-bits of the retrieved data word the upper 32-bit device (112) generates, new, correction partial check bits. Further, responsive to the new correction partial check bits and to the state of the correction partial syndrome-bit signals (developed by lower 32-bit device 110 on inter-device bus 124) the upper 32-bit device (112) is operative to generate full syndrome bits and to develop, on the syndrome/check bit bus (122), signals representing the full syndromes. Finally, responsive to the state of the latched, upper 32-bits of the retrieved data word and to the full syndromes, the upper 32-bit device (112) corrects errors in the latched, upper 32-bits of the data word and develops, on the upper 32-bit data bus (130), signals representing the corrected, upper 32-bits of the data word. Finally, responsive to the state of the latched, lower 32-bits of the retrieved data word and to the signals representing the full syndromes (developed by upper 32-bit device 112 on syndrome/check bit bus 122) the lower 32-bit device (110) corrects errors in the latched, lower 32-bits of the data word and develops, on the lower 32-bit data bus (120), signals representing the corrected, lower 32-bits of the data word.
It is important to note that, when a pair of the above-mentioned (49C460 type) devices are so configured (for word expansion), when a word of data is being retrieved from memory, developed on the syndrome/check bit bus (122) are signals representing the retrieved check bits followed by signals representing the full syndromes. As a consequence, when so configured, the above-mentioned (49C460 type) devices are relatively slow (have relatively high propagation delays) and require relatively complex (control) circuitry (for developing the requisite control signals).
For additional information regarding the above-mentioned (49C460 type) devices and the generation of the Hamming code type check bits and syndrome bits they employ, the reader is referred to the above-mentioned 49C460 data sheets and/or the above-mentioned "High Performance CMOS 1988 Data Book." Other prior-art-type error detection and correction devices include those of the type which are designated 8206 by Intel Inc., those of the type which are designated DP8400-2 by National Semiconductor Inc., those of the type which are designated MB1426 by Fujitsu Inc., and those of the type which are designated SN54ALS632B by Texas Instruments Inc.